This invention generally relates to semiconductor device manufacturing methods and more particularly to methods for improving adhesion of a capping layer with reduced dielectric constant with overlying low-k dielectric insulating materials.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic effects of insulating materials in which metal interconnects are formed to interconnect devices. It has become necessary to reduce capacitance of the insulating layers to allow the insulating layer thicknesses to shrink along with other device features such as metal interconnect line width. As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials.
In the fabrication of semiconductor devices multiple layers may be required for providing a multi-layered interconnect structure. During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers.
Manufacturing processes such as, for example, damascene processes, have been implemented to form metallization vias and interconnect lines (trench lines) by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple layers of metallization vias and interconnect lines. For example, in the dual damascene process, a trench opening and via opening is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a substrate including another conductive area over which the vias and trench lines are formed and in communication with. After a series of photolithographic steps defining via openings and trench openings, via and the trench openings are filled with a metal, preferably copper, to form metallization vias and interconnect lines (trench lines), respectively. The excess metal above the trench line level is then removed by well known chemical-mechanical planarization (polishing) (CMP) processes.
As indicated, advances in semiconductor device processing technology demands the increasing use of low-k (low dielectric constant) insulating materials in, for example, IMD (ILD) layers that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials has become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants less than about 3.0 for achieving integration of, for example, 0.13 micron interconnections. In the future, even lower dielectric constant material, for example less than about 2.5, will be required for 0.1 micron process integration. An exemplary low-k inorganic material that is frequently used, for example, is carbon doped silicon dioxide (C-oxide) formed by a CVD process where the dielectric constant may be varied over a range depending on the process conditions. C-oxide, for example, may be formed with dielectric constants over a range of about 2.0 to about 3.0 and density of about 1.3 g/cm3 compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm3 for silicon dioxides (e.g., un-doped TEOS). Other exemplary low-k inorganic materials include porous oxides, xerogels, or SOG (spin-on glass). Exemplary low-k organic materials include polysilsequioxane, parylene, polyimide, benzocyclobutene and amorphous Teflon.
Regardless of whether, the low-k insulating material is organic or inorganic, the presence of porosity, for example, mesoporosity, is generally required to achieve the desired low dielectric constant of between about 2.0 and about 3.0.
As might be expected, the development of porous low-k materials has presented several problems in manufacturing methods that must be overcome. Among the problems presented by porous materials, especially if they are hydrophilic, is the tendency to absorb moisture which may interfere in subsequent dry etching processes. Another problem is the tendency of porous materials, especially those with interconnecting pores, is to absorb chemical species, for example, nitrogen containing species present in CVD processes to form capping or etch stop layers, of for example, silicon nitride (SiN) or silicon oxynitride (SiON), over the insulating layers and such species believed to interfere with subsequent photolithographic processes.
Another important limitation is that porous low-k materials have low strength and are subject to cracking or peeling in subsequent manufacturing processes including, for example, chemical mechanical planarization (CMP). In order to protect the porous low-k insulating material layers, it has been the practice to add a capping layer over the insulating layer such as a metal nitride including for example, silicon nitride (SiN) and silicon oxynitride (SiON). Additionally, silicon carbide (SiC) has been used as a capping layer to protect the insulating layer in subsequent processing steps including CMP. One problem with the prior art capping layer technology is that due to the high porosity present in low-k insulating materials, adhesion between the capping layer and the insulating layer has proven to be poor, resulting in, for example, peeling, when subjected to the stresses of CMP. Another problem has been that the capping layer adds to the overall dielectric constant and therefore capacitance of the multilayer device making it desirable to make the capping layer as thin as possible, with the undesirable corresponding consequence of current leakage between metal interconnect lines.
It would therefore be advantageous to develop a method for forming a capping layer for use over a porous low-k insulating material layer in a multiple layer semiconductor device that has improved adhesion to the low-k insulating material while additionally having a lower dielectric constant compared to conventional capping layer materials, yet achieves at least the same degree of electrical isolation.
It is therefore an object of the invention to present a method for forming a capping layer for use over a porous low-k insulating material layer in a multiple layer semiconductor device that has improved adhesion to the low-k insulating material while additionally having a lower dielectric constant compared to conventional capping layer materials while overcoming other deficiencies and shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process.
In a first embodiment, the method includes providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.